1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit and an optical disc apparatus.
2. Description of Related Art
An optical disc apparatus for recording and reproducing data to and from an optical disc media such as CD and DVD is widely used at the moment. Spirals (wobble) of a predetermined cycle are fabricated in grooves formed on the disc surface of an optical disc media. An optical disc apparatus provides a wobble signal (hereinafter referred to as a rotation synchronizing signal) generated according to this wobble to a PLL circuit, and generates a synchronous clock signal at the time of record and reproduction. The frequency of this rotation synchronizing signal is different between the outer and the inner circumstance of a disc.
Therefore, the optical disc apparatus includes a PLL circuit which fluctuates the frequency of a synchronous clock signal according to the rotation synchronizing signal. In order to accurately record and reproduce data to and from an optical disc media, such PLL circuit needs to generate a clock signal which synchronizes with a target clock signal with high phase accuracy.
An example of the PLL circuit which generates a clock signal synchronized with a reference signal accurately is disclosed in Japanese Unexamined Patent Application Publication No. 2008-205730. FIG. 17 illustrates the configuration of a PLL circuit 1 disclosed in Japanese Unexamined Patent Application Publication No. 2008-205730. As illustrated in FIG. 17, the PLL circuit 1 includes a polyphase reference clock output circuit 10, a digital VCO (Voltage Controlled Oscillator) 20, a selection circuit 30, a frequency control terminal 40, and a high precision clock output terminal 50.
The polyphase reference clock output circuit 10 includes odd number of inverter circuits IV1 to IV7. The inverter circuits IV1 to IV7 are connected in series sequentially, and an output of the last stage inverter circuit IV7 is connected with an input of the first stage inverter circuit IV1. Outputs from the inverter circuits IV1 to IV7 are input to the selection circuit 30 as polyphase reference clocks CK1 to CK7, respectively.
The digital VCO 20 outputs an output clock OCK including a frequency which fluctuates according to the value of a frequency control input Mf which is input from the frequency control terminal 40, and delay amount data which indicates a phase difference between the phase of an ideal clock calculated according to the value of the frequency control input Mf, and the phase of the abovementioned output clock OCK. This digital VCO 20 operates with the reference clock CK1 as an operating clock.
The selection circuit 30 includes multiple D flip-flops FF1 to FF7 and a selector SEL1. The output clock OCK is input to each data input terminal D of the D flip-flops FF1 to FF7. Further, the reference clocks CK1 to CK7 are input to each clock input terminal of the D flip-flops FF1 to FF7. Then, each data output terminal Q outputs delay clocks F1 to F7 at rising edges of the reference clocks CK1 to CK7. The selector SEL1 selects one of the delay clocks F1 to F7 according to the delay amount data, and outputs the selected delay clock to the high precision clock output terminal 50.
Such PLL circuit 1 can output a high precision clock which includes high phase precision to the clock signal which should be output from the high precision clock output terminal 50.